5. Vref Relation to Vin Range for an 8-bit
ADC
Vref (V) Vin in Range (V) Step Size (mV)
5.00 0 to 5 5 / 256 = 19.53
4.00 0 to 4 4 / 256 = 15.62
3.00 0 to 3 3 / 256 = 11.71
2.56 0 to 2.56 2.56 / 256 = 10
2.00 0 to 2 2 / 256 = 7.81
1.28 0 to 1.28 1.28 / 256 = 5
1.00 0 to 1 1 / 256 = 3.90
Note: In an 8-bit ADC, step size is Vref/256
5
6. Vref Relation to Vin Range for an 10-bit
ADC
Vref (V) VinRange (V) Step Size (mV)
5.00 0 to 5 5 / 1024 = 4.88
4.96 0 to 4.096 4.096 / 1024 = 4
3.00 0 to 3 3 / 1024 = 2.93
2.56 0 to 2.56 2.56 / 1024 = 2.5
2.00 0 to 2 2 / 1024 = 2
1.28 0 to 1.28 1.28 / 1024 = 1.25
1.024 0 to 1.024 1.024 / 1024 = 1
Note: In a 10-bit ADC, step size is Vref/1024
6
7. ADC STM32
Formas de llamar el ADC:
● Polling
● Interrupción
● DMA
Tipo de conversión:
● Un solo canal
● Múltiples canales
● Un solo canal, múltiples muestras
8. /* USER CODE BEGIN 1 */
uint16_t AD_RES = 0;
uint8_t MSG[35] = {'0'};
/* USER CODE END 1 */
while (1)
{
HAL_ADC_Start(&hadc1);
HAL_ADC_PollForConversion(&hadc1, 1);
AD_RES = HAL_ADC_GetValue(&hadc1);
sprintf(MSG,"%drn", AD_RES);
HAL_UART_Transmit(&hlpuart1, MSG, sizeof(MSG), 100);
HAL_Delay(100);
/* USER CODE END WHILE */
Inicia la conversión
Polling (Bloquea)
hasta que termina
la conversión
Copia el resultado
15. RCC_APB2ENR (RCC APB2 peripheral clock enable
register) to enable clock to ADC
15
Bit 10 ADC3EN: ADC3 clock enable
This bit is set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled
Bit 9 ADC2EN: ADC2 clock enable
This bit is set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock disabled
Bit 8 ADC1EN: ADC1 clock enable
This bit is set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock disabled
16. ADC sample time register (ADC_SMPR1)
to set sampling time
16
000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
17. ADC sample time register (ADC_SMPR2)
to set sampling time
17
000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
19. ADC bit Resolution Selection in ADC_CR1 register
19
RES (bits 25-24) Description
0x0 12-bit result
0x1 10-bit result
0x2 8-bit result
0x3 6-bit result
22. GPIO_MODER Register
22
Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode
23. ADC_DR (ADC Data Register) register holds conversion
result
23
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
These bits are read-only. They contain the conversion result from the regular channels.
The data are left- or right-aligned.
25. ADC_CR2 (ADC Control 2) register
25
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 75 and Figure 76.
0: Right alignment
1: Left alignment
Bit 10 EOCS: End of conversion selection
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until
it is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
Note: 0: Disable ADC conversion and go to power down mode
1: Enable ADC
27. ADC_SR (Status) Register Bits
27
Bit Field Descriptions
5 OVR Overrun This bit is set by hardware when data are lost. This happens if we
do not read the result of the last conversion from the Data Register
(ADC_DR). It is cleared by software.
0: No overrun occurred
1: Overrun has occurred
1 EOC End of Conversion
0: Conversion not complete
1: Conversion complete
Writing a zero to this bit will clear it or by reading the ADC_DR register.
30. ADC common control register (ADC_CCR) register
30
Bit Field Descriptions
22 TSVREF
E:
Temperature Sensor and VREINT Enable
This bit is set and cleared by software to enable/disable the temperature sensor
and the VREFINT channel.
0: Temperature sensor and VREFINT channel disabled.
1: Temperature sensor and VREFINT channel enabled.
23 VBATE:
VBAT
enable
VBAT enable
0: VBAT channel disabled.
1: VBAT channel enabled.
17:1
6
ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The
clock is common for all the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
31. Thermistor Resistance vs. Temperature
Temperature ('C) Tf (K ohms)
0 29.490
25 10.000
50 3.893
75 1.700
100 0.817
31