provides architectures of major processors used in smart phones

1. Dr. Rajveer S Shekhawat
GM, New Products Development,
Secure Meters Ltd

2. Performance and Power Challenges to
mobile computing
HD Video playback
Steaming audio & video
3D Gaming
3D interfaces
Web browsing
Multiple application
Location-based services (maps and satellite images)
So single processors are being replaced by multicore
processors to meet the above requirements.04/07/15 CMCTAR2012 2

3. Predictions
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5. Major Mobile Devices using
MCPs
Smart phones
PDAs
Tablets
Laptops
Game Stations
Vehicle navigation systems
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6. Performance Challenges
Multi core architectures with high integration of
peripherals are needed to deliver ever increasing
performance. The likely peripherals are:
Graphics/image/video
Voice/speech
Intelligent keys/trackballs
3D motion
GPS
Communication (Bluetooth, WiFi, IR, GSM/UMTS)
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7. Challenge areas
Hardware
Architecture
Computation
Speed
Power
Complexity
Graphics
speech
Software
System programming
Application programming
User interface
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8. Cost Optimization
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9. Power Optimization
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17. Parallel Programming
Multi-core architectures can help in reducing power
consumption of single CPU to increase computational
power. However to best make use of them, we need to
write efficient parallel programs for both systems and
application programming. This area is still evolving
and needs better programming tools to support faster,
accurate and efficient programs.
Multi-core processors can have two configurations:
 Symmetric multiprocessing (SMP)
 Assymetric multiprocessing (ASMP)
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18. Symmetri Multi Processing
SMP architecture consists of two or more identical
CPU cores.
All cores share a common system memory and are
controlled by a single Operating system.
Each CPU is capable of operating independently on
different workloads and whenever possible, is also
capable of sharing workloads with the other CPU.
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19. Example
NVIDIA Tegra 2 and Tegra 3
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22. Architectural Features of Tegra 2
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 Dynamic length 8-stage pipeline supporting speculative out-of-order
execution. This allows the processor to dynamically reorder instructions to
improve performance by avoiding stalls due to instruction latencies and
resource conflicts. Older generation Cortex-A8 processors use an in-order
pipeline and are unable to avoid the penalties that arise from branching and
cache misses support for speculative branch predictions to avoid branching
penalties.
 A Dual-core Symmetrical Multiprocessing (SMP) configuration operating
either independently, or in lockstep to deliver peak performance when
needed, and consuming almost zero power when idle.
 32KB Instruction cache and 32KB Data cache per core with both cores sharing
a common 1MB L2 Cache. The 1MB L2 cache is large enough to load an entire
browser memory footprint into cache to provide a faster Web browsing
experience.
 CPU cores that are optimized to operate at a frequency of one Gigahertz with
the ability to scale up to even higher frequencies. The two cores are assisted
by a common snoop control unit that enforces coherency between the cores
and manages the common 1MB L2 cache shared by the two cores.

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24. Intelligent Power Management
Long battery life along with high computing power is
only feasible if we can use multi-core architectures
with low power consumption. A popular technique is
Dynamic Voltage and Frequency Scaling (DVFS).
Here the voltages (both supply and threshold) can be
reduced to for lower power operation. Further
frequency of operation can also be scaled down.
However, to keep the execution timing of tasks intact,
multitasking/mutit-threading can be used. There
appropriate scheduling algo’s for multi-cores.
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26. Tegra 3 from Nvidia (vSMP)
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27. Renesas Dual Core (EMMA)
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28. EMMA Features
It is an application processor for smart mobiles.
It has two ARM Cortex-9 cores with two Neon
extensions
It has an integrated audio/video engine,
A 3D graphics block
A number of communication interfaces
It uses hardware accelerator for HD quality decoding
It consumes minimal power
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32. Expectations (PwC report)
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33. Parallel Programming
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35. Common Prog Environs
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36. Thanks
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