This poster by Steffen Zeuch presents our VLDB 2019 full research paper about "Analyzing Efficient Stream Processing on Modern Hardware". We analyzed state-of-the-art stream processing engines and investigated the data-related and processing-related design space. Form that, we derive design changes for streaming systems to exploit modern hardware more efficiently. We show that a speedup of two orders of magnitude is possible using these design changes. The full paper is available online: http://www.vldb.org/pvldb/vol12/p516-zeuch.pdf

1. Analyzing Efficient Stream Processing
on Modern Hardware
We analyzed state-of-the-art SPEs Take Home
Can we ingest data at memory speed?
Steffen Zeuch, Bonaventura Del Monte, Jeyhun Karimov,
Clemens Lutz, Manuel Renz, Jonas Traub, Sebastian Breß,
Tilmann Rabl, Volker Markl
What performance possible?
What is the design space for an SPE?
Scale-up Experiment Scale-out Experiment
Why are current SPEs inefficient?
Investigate data-related and
processing-related design space
Two orders of magnitude speedup is possible
Derive design changes for streaming systems
to exploit modern hardware more efficiently
Data ingestion at memory speed is possible There is a lot of scale-up potential
Current SPEs exploit modern hardware insufficiently Scale-up solution outperforms 10 node cluster
Code footprint and scatterd access patternFor scale-up, there is more than partitioning
Current SPEs are not yet ready
for upcoming ingestion rates
Large instruction footprints and
suboptimal access patterns reduce efficiency
Current SPEs do not exploit modern
hardware efficiently