Final Year Report (6bits DACs)

Bachelor of Engineering / Science
Electronic Engineering
Final Year Project Report
6-bit Current Steering Thermometer DAC
Lee Siang Wei
W20065233
Bachelor (Hons) Degrees In Electronic Engineering
Academic Year 2015/2016
Department of Engineering Technology
School of Engineering
Waterford Institute of Technology,
Ireland.

Final Project Thesis WIT BEng (Hons) Electronic Engineering – 2015/16
Table of contents
Acknowledgement...........................................................................................................i
Abstract…………..........................................................................................................ii
Section I: Introduction.......................................................................................1-5
1.1 Digital to Analogue Converter
1.2 Objective of Thesis
1.3 Design Specifications
1.4 Thesis Organization
Section II: Background…………………….....................................................6-15
2.1 Binary and Thermometer Decoder
2.2 MSBs and LSBs Current Source
2.2.1 Unary DACs
2.2.2 Binary DACs
2.2.3 Binary Weighted Architecture VS. Unary Decoded
Architecture
2.2.4 Segmented DAC Based thermometer DACs
Section III: Design and Architecture………………………………………...16-31
3.1 Thermometer Decoder
3.1.1 Logic NOT gate
3.1.2 Logic OR Gate
3.1.3 Logic AND gate
3.1.4 3-Inputs OR gate and 3-Inputs AND gate
3.1.5 MSBs and LSBs Thermometer Decoder
3.2 Current Source DAC
3.2.1 LSB DAC
3.2.2 MSB DAC
Section IV: Simulation Result………………………………………………..32-35

Section V: Conclusion................................................................................................36
References...................................................................................................................37
Appendices.............................................................................................................38-43

Final Year Project Report WIT BEng (Hons) Electronic Engineering – 2015/16
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ACKNOWLEDGEMENT
Firstly, I would like to express my sincere gratitude to my final project supervisor
who is also Group Leader of Microelectronics and Systems Research Group, Kenneth
Deevy for his positive attitude showed to my work and supervision that truly helps the
progression and smoothness of this internship program. The co-operation is much
indeed appreciated. I could not have imagined having a better advisor and mentor for
my thesis study.
Last but not least, I would like to express my heartfelt gratitude to my family
members for their support, concern and love. A paper is not enough for me to express
the support and guidance I received from them almost for all the work I did there.

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ABSTRACT
This paper presents the design, architecture and simulation result of 6-bit Current
Steering Digital to Analogue Converter (DAC) architectures. The DAC has been
implemented in 3+3 Segmentation to achieve maximum performance with minimum
area. The segmented architecture is applied using two sets of Thermometer DAC’s,
which are the LSB and MSB section with certain number bits. The DAC is designed
using 6-bit Thermometer-coded DAC for the LSB section MSB section. The
thermometer-coded architecture offers the most optimized results in terms of linearity
through reducing the clock feed-through effect especially in switching between
multiple transistors. The project design is based on a differential current steering
topology. The differential output of the DAC is loaded with resistor and a full-scale
differential voltage of 1.26Vpp is generated. This type of converter is suitable for
high-speed D/A converters because almost all current goes through the output, instead
of turning a current off that might cause the inductive spikes.

1
I INTRODUCTION
Digital signal processing has been applied into more and more applications with the
use of VLSI (Very Large Scale Integration) technology. Many applications which
have been implemented in analogue domain have been moved to digital, such as
wireless mobile phones. Nowadays, most of the integrated circuits have both analogue
and digital circuits which also known as mixed-signal integration. The analogue and
digital integrated circuits were designed and made-up in different technologies.
Typically, analogue circuits use bipolar technologies, while digital circuits are in
MOS (Metal Oxide Semiconductor) technologies. CMOS technology dissipates less
power compare to other design. CMOS architecture can be easily scaled down for the
major three factors:
 Area
 Speed
 Power
Hence, CMOS technologies become majority technologies for mixed-signal
integration due to the benefits of high speed, low power and high integration density.
CMOS technology scaling has been a primary driver of the electronics industry and
has provided a path toward both denser and faster integration. Moreover, it also
proved to have a low fabrication cost. The low cost of fabrication and the possibility
of placing both analogue and digital circuits on the same chip so as to improve the
overall performance and reduce the cost of packaging made CMOS technology
attractive.

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1.1 Digital to Analogue Converter
Nowadays, the world is getting digitalised, but the signal we notice and retain is in
analogue form. In order to process the signal effectively we have to convert it into
digital. After processing them, we need to convert it back to obtain real world which
is analogue signal. This phenomenon has led to development of data converters
which is a medium that perform conversion between analogue world and digital world.
In Electronics, Digital to Analogue Converters (DAC‘s) converts a digital (usually
binary) code to an analogue signal (current, voltage, or electric charge). Although the
signal are easily stored and transmitted in digital form, a DAC is needed for the signal
to be recognized by human senses or other non-digital systems. A common use of
Digital to Analogue Converter is generation of audio signals from digital information
in music players. Meanwhile, the digital video signals are also converted to analogue
form in the screen of televisions and mobile phones to display colours and shades.
Digital to analogue conversion can degrade a signal, so conversion details are
normally chosen so that the errors are insignificant. Due to cost and the need for
matched components, DACs are almost exclusively manufactured on Integrated
Circuits (ICs). There are many DAC architectures which offer different advantages
and disadvantages. The suitability of a particular DAC for an application is
determined by a variety of measurements including speed and resolution. In order to
achieve high speed operation and low power consumption, the current steering type is
the most widely used design technique.
One of the more used architectures to design MOSFET-only DAC is based in the
current source techniques using an array of matched current sources. They are
frequently used to achieve high linear devices, using segmented architectures and

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proper switching scheme. A large number of transistors have to be applied (to achieve
N bit linearity, we need 2N
transistors without any segmented architecture) in order to
achieve this high linearity, and geometrical matching of the structure becomes
significant in order to reduced undesired nonlinearly.
The output of a DAC may be a voltage or a current. In either case it may be important
to know the output impedance. If the voltage output is buffered, the output impedance
will be low. Both current outputs and un-buffered voltage outputs will be high
impedance and may have a reactive component specified as well as a purely resistive
one. In theory, current outputs should be connected to 0 ohms at ground potential. In
real life they will work with non-zero impedances and voltages. Just how much
deviation they will tolerate is defined under the heading "compliance" and this
specification should be observed when terminating current-output DACs.
1.2 Objective of Thesis
In this thesis work, 6-bit Current Steering Digital to Analogue Converter (DAC) with
using only MOSFETs is proposed. This is because using of resistors in DAC might
difficult to fabricate with reasonable layout size, and also the resistor value sometimes
could be difficult to predict. Also, MOSFET DAC‘s are intrinsically faster and more
linear than resistor-string DACs. The goal of the thesis work is to design a segmented
DAC based on 2 set of 3-Bit Thermometer DACs for high speed applications.

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1.3 Design Specifications
This design chooses unit-element current source topology. There are 2 major parts in
this design:
 Binary to Thermometer Decoder
 MSB and LSB Current Source
6-bit digital inputs‘ glitches can be removed by thermometer decoder; they are
changed to 23+3
thermometer signals. These signals perform as controlled codes to
determine how many current cells are on/ off and the values of IOUT and IGND. Active
current sources are used as shown in Fig 1 below, the output may have more
compliance, and a resistive load used to develop an output voltage. The load resistor
must be chosen so that at maximum output current the output terminal remains within
its rated compliance voltage. Once a current in a thermometer DAC is switched into
the circuit by increasing the digital code, any further increases do not switch it out
again. The structure is thus inherently monotonic, irrespective of inaccuracies in the
currents. Finally, the total output current is then multiply with resistor value to serve
as the analogue output.

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Fig 1: 6-bit Segmented Current Steering Digital to Analogue Converter (DAC) with MSB and
LSB Thermometer DACs
1.4 Thesis Organization
The thesis work is documented as shown below.
 Section II: explains technical review on the Binary to Thermometer Decoder
and MSB and LSB Current Source
 Section III: presents the design and architecture of 6-bit Current Source Digital
to Analogue Converter
 Section IV shows the simulation results of 6-bit Current Source Digital to
Analogue Converter
 Section V draws conclusions and future discussion on the work.

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II TECHNICAL REVIEW
2.1 Binary-to-Thermometer Decoder
With current source DACs, switches are used as a path to drive current into current
sources. The switches are driven by the digital binary value representing the number
to be converted to analogue. It simply means that how much the amount of current
sensed would become the analogue value. However, any high speed DAC will
produce a glitch when it changes from one voltage to another. These glitches are
relative small voltage spikes which occur when the DAC outputs a new voltage level.
When there is a changing on digital binary values, it might cause some switches open
and others close. Obviously, it could have a mismatch between the ―make‖ time of the
closing switches and the ―break‖ time of the opening switches. As a result, this ends
up generating a glitch at the output and it could definitely affect the dynamic
performance of DAC.
Fig 2.1 DAC glitch behaviours
Thermometer code is used to get rid of this problem. Thermometer code is one
method to representing information that is to be presented to a non-natural neural
network and typically used to perform a quantitative variable. As shown in Fig 2.2,
the Thermometer output is just like some kind of stair when increasing the binary
input. Given a binary value of "010" which is also decimal of ‗2‘, the first two input
units would be triggered (1100000); In order to represent a binary value of "011", the

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first three input units would be triggered (1110000), and so on. That is why it called
as thermometer code, as the input units resemble a thermometer placed on its side,
with the "height" of the "mercury" in the thermometer representing the value of the
input variable. If you turned it 90 degrees with the LSB at the bottom, then, as the
number increased or decreased, the place where the 1s stop would rise and fall just
like the mercury in an old thermometer. The order of turn-on relative to ascending
code changes for each new data point. This can be done quite easily with a little extra
logic in the decoder.
Fig 2.2: Actual Thermometer Output with Binary Input
The benefit of thermometer code is that, the changing switches are either all opening
or all closing when there is a change in value. There‘s no mix of opening and closing
switches, and produce no glitches at the output. Therefore, the 3 bit Binary to
Thermometer decoder works what its name as, converts 3 digital binary codes to
thermometer ones. Thermometer coding is used in some high speed DACs that shown
in the Fig 2.3 below. More detailed information on current output DAC I will discuss
in Section 2.2.

8
Fig 2.3: High Speed Thermometer DAC with Complementary Current Outputs
2.2 MSBs and LSBs Current Source DAC
The current source DAC, which is based on the switched-current technique, is
appropriate for high-speed applications and, therefore, the most frequently used DAC
architecture in wideband communication applications. Current source DACs are a
more common integrated DAC compared to resistor DACs due to their small size and
simplicity. This is because the size of resistor is bigger makes it harder to fabricate
with reasonable layout size, and also the resistor value sometimes could be difficult to
predict.
Therefore, current source DAC replaces the resistor element in the resistor DAC
architectures by using a MOSFET current element and uses some form of addition of
the current elements to produce the output. Sometimes the result needs to be a current
such as in integrated bias circuits. This current is then passed to the next stage of a
current mirror bias or passes through a MOSFET stack to produce a set of current
mirror bias voltages. Voltage-mode DACs convert the current to voltage with a

9
simple resistor for improved linearity, as shown in Fig 2.7 below. While, current
source DACs are much more prefer due to the lower space used by MOSFET current
elements and the ability to perform some calibration tricks.
Fig 2.7 (a) Non-inverting and (b) inverting current source DAC architecture
2.2.1 Unary DACs
Unary current DACs also called as thermometer coded DACs, use a single-current
element for each quantization step. The reference elements are all equally same and
the matching of the individual elements becomes simpler than for the binary case. The
total sum of all weights is 2N
-1. An 8-bit thermometer DAC would have 255 segments,
and a 16-bit thermometer DAC would have 65,535 segments. This is perhaps the
fastest and highest precision DAC architecture but at the expense of high cost. The
transfer function of the thermometer coded converter is monotonic and the DNL and
INL are improved compared to the binary version.
Unary current DACs are similar to resistor divider DACs with a resistor element for
each LSB. Bit of a digital control word controls a switch that steer the current from
the current source to one of the load resistors. Consequently, these DACs are
inherently monotonic, but they consume a large area for medium to high resolutions.
In Fig 2.8, Iu is a single unit current and Tx is the thermometric equivalent of the
binary input. As I mentioned thermometer decoder in Section 2, a binary input of
00…000 leave all switches open. If we had a binary input of 00…011, or equal to

10
decimal value of 3, then T0, T1, and T2 switches would be closed, and the rest of the
switches would be still open.
Fig 2.8 Typical Unary Current Divider DAC
2.2.2 Binary DACs
The binary DAC, which contains individual electrical components for each bit of the
DAC connected to a summing point. These precise voltages or currents sum to the
correct output value. This is one of the fastest conversion methods but suffers from
poor accuracy because of the high precision required for each individual voltage or
current. Such high-precision components are expensive, so this type of converter is
usually limited to 8-bit resolution or less. Binary current DACs gather current
elements into binary multiples that are turned on or off directly with the input bits.
However, binary DACs frequently use individual unit current sources to make up the
larger binary units for matching purposes. For instance, the 2 x Iu element would be
composed of two identical Iu elements. This results in binary DACs being composed
of the same number of current elements. Nevertheless, it is entirely possible to simply
change the transistor aspect ratios to achieve the binary current multiples instead of
exactly repeating the unit current element. This will cause the DACs in more
nonlinearity, in exchange for a much smaller layout area. This technique will produce

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nonlinearity which is worst between switch points such as 011…11 switching to
100…00.
2.2.3 Binary Weighted Architecture VS. Unary Decoded Architecture
Current source DACs are based on an array of matched current sources which are
unity decoded or binary weighted. As shown in Fig 2.9, the reference source is simply
simulated in each branch of the DAC, and each branch current is switched on or off
based on the input code. For the binary version, the reference current is multiplied by
a power of two, creating larger currents to represent higher-magnitude digital signals.
In the thermometer version, each current branch produces an equal amount of current,
and thus 2N
current source elements are needed.
Fig 2.9: One Dimensional Current Steering Thermometer and Binary DAC
The performance of the DAC is determined by specific parameters:
 Integral Non-Linearity (INL)
 Differential Non-Linearity (DNL)
 Parametric yield
 Glitch energy
 Settling time

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 SFDR.
Static performance is mainly dominated by systematic and random errors. Systematic
errors caused by process, temperature and electrical slow variation gradients are
almost cancelled by proper layout techniques. Random errors are determined solely
by mismatch due to fast variation gradients. Unary and binary current DACs are often
used together. Typically, unary DACs are used for the MSB current elements because
of their inherent monotonicity. Binary DACs are used for the LSB elements because
of their much smaller size when created with weighted transistors. Advantages and
disadvantages of these structures are summarized below:
Thermometer DACs Binary DACs
 Low glitch energy
 Monotonicity
 Small DNL errors
Advantages
 Low digital power
consumption
 Small number of control
signals
 Digital decoding with more
area and power consumption
 Increased number of control
signals
Disadvantages
 Monotonicity not guaranteed
 Larger DNL errors
 Large glitch energy
In order to match the requirement for my design which is 6-Bit Current-Output
Segmented DAC, Thermometer DACs is selected due to its low glitch energy,
monotonicity and small DNL errors. In this design, the thermometer decoder is
divided into two parts, one for 3 MSBs and another 3 LSBs with each having 3 inputs
and 7 outputs, 63 thermometer coded output is required.

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2.2.4 Segmented DAC Based thermometer DACs
As we all know, there is no single DAC architecture is ideal when we are required to
design a DAC with a certain performance. In order to get optimum performance, two
or more DACs may be combined in a single higher resolution DAC to give the
required performance. These DACs need not necessary to have the same resolution
and may be of the same type or of different type. It means that, one DAC handles the
MSBs, another handles the LSBs, and their outputs are added in some way. The
process is known as "segmentation," and the structures are known as "segmented
DACs".
There are many different types of segmented DACs and some. Very high speed DACs
for video, communications and other HF reconstruction applications are often built
with arrays of fully decoded current sources. The two or three LSBs may use binary-
weighted current sources. It is extremely important that such DACs have low
distortion at high frequency, and there are several important issues to be considered in
their design. Firstly, currents are never turned on and off—they are steered to one
place or another. Turning a current off at high speed frequently involves inductive
spikes and, in general, because of capacitance charging, it takes longer than current
steering. Secondly, the voltage change on the chip required to switch the current
should always be kept as small as possible. This is because a minor voltage change
might result in more charge to flow in stray capacitances and a larger charge-coupled
glitch. Finally, the decoding must be completed before the new data is applied to the
DAC. The purpose of this is to provide the sufficient time for all the data to ready
and then can be applied simultaneously to all the switches in the DAC. This is
generally implemented by using separate parallel latches for the individual switches in

14
a fully decoded array. If all switches were to change state instantaneously and
simultaneously there would be no skew glitch.
There is a current-output DAC analogous that consists of 2N
–1 switchable current
sources connected to an output terminal. This architecture is commonly referred to as
a "thermometer" or "fully decoded" DAC. A 3 Bit Thermometer DAC which the
currents are switched between two output lines, where one of which is often grounded
or can be used as the inverted output. This architecture is shown in Fig 2.10. In the
linear version of this DAC, all the currents are supposedly equal. Where it is used for
high speed reconstruction, its linearity can be improved by dynamically changing the
order in which the currents are switched by ascending code. As previously discussed,
binary value of 001 will always turning on current A; then 010 always turning on
currents A & B, and 011 always turning on currents A, B & C and soon on.
Fig 2.10: Thermometer DAC with Complementary Current Outputs
The segmented DAC in this thesis is 6 Bit DAC, fully used of the 3 bit thermometer-
coded principle for both the most significant bits (MSB) and least significant bits
(LSB). This architecture is commonly stated as a "thermometer" or "fully decoded"
DAC as shown in Fig 2.11. This DAC consists two output lines where the currents are

15
switched between of them, one of which is often grounded, and also can be used as
the inverted output. It is more suitable for high speed applications because switching a
current between two outputs is less disruptive, and so causes a lower glitch than
simply switching a current on and off. As previously discussed, these current switches
must be driven simultaneously from parallel latches in order to minimize the output
glitch.
Fig 2.11: 6-Bit Current-Output Segmented DAC Based on Two 3-Bit Thermometer DACs
Hence, in terms of the number of switched unit current sources, the fully
thermometer-coded architecture is an optimum solution. However, using a fully
thermometer-coded architecture might result in a large hardware complexity. For
example, we have 214
-1 which is 16 383 bits in the control word yielding equally
many control wires and switches and a complex routing of wires. Hence, there is a
trade-off between performance and hardware complexity. It should be mentioned that
there exist variations on the segmented architecture. For example, several groups of
bits in the input may be encoded into thermometer codes with different weights. An
example is the segmented 14-bit DAC for which both the 7 MSBs and the 7 LSBs are
encoded into thermometer code.

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III DESIGN AND ARCHITECTURE
According to the logic truth table below, the logical relationship can be expressed as
follows:
Fig 3.0 Truth table for Binary-to-Thermometer Decoder
‗D2‘ is the most significant bit (MSB) and ‗D0‘ is the least significant bit (LSB) of
binary codes while S1 is LSB and S7 is MSB of thermometer codes. The schematic of
this decoder based on the truth table is in Fig 3.1. Each symbol represents a lower
level schematic, for example
 3 bits OR gate is used for S1 in order to OR 3 inputs of D0, D1 and D2
 3 bits AND is used for S7 to AND 3 inputs of D0, D1 and D2
NOT gate are added to obtain similar delay time in every branch of the decoder‘s
output while retain the same logic. In this report, CMOS is used instead of 74HC
families in order to create the logic gate for AND, OR and NOT gate due to its low
power consumption. The Hierarchy block is built based on the truth table above with
the logic gate for AND, OR, and NOT gate for the thermometer decoder is shown in
the Fig 3.2.

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Fig 3.1: Schematic of 3-Bit Binary-to-Thermometer Decoder
Fig 3.2 Hierarchy Block Diagram for 3-Bit Binary-to-Thermometer Decoder

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3.1.1 Logic NOT gate
The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes
referred to as an Inverting Buffer or simply a Digital Inverter. It is a single input
device which has an output level that is normally at logic level ―1‖ and goes ―LOW‖
to a logic level ―0‖ when its single input is at logic level ―1‖, in other words it ―inverts‖
(complements) its input signal. The output from a NOT gate only returns ―HIGH‖
again when its input is at logic level ―0‖ giving us the Boolean expression of: ̅ .
The NOT gate can be built up from PMOS on the top and NMOS on the bottom as
shown in Fig 3.3.
Fig 3.3 NOT gate with PMOS on top and NMOS on bottom
If input I are ―high‖ (1), the NMOS will be saturated, thus driving the ground (0V) to
the output to go ―low‖ (0). In the event of inputs I being ―low‖ (0) will cause the
NMOS be in cut-off mode and PMOS be saturated, then drives the VDD (5V) to the
output to go ―high‖ (1). The Table 1 shows the truth table for NOT gate.
Input Output
0 1
1 0
Table 1

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3.1.2 Logic OR Gate
A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has an
output which is normally at logic level ―0‖ and only goes ―HIGH‖ to a logic level ―1‖
when one or more of its inputs are at logic level ―1‖. The output, Q of a ―Logic OR
Gate‖ only returns ―LOW‖ again when ALL of its inputs are at a logic level ―0‖. In
other words for a logic OR gate, any ―HIGH‖ input will give a ―HIGH‖, logic level ―1‖
output. The logic or Boolean expression given for a digital logic OR gate is that for
Logical Addition which is denoted by a plus sign, (+) giving us the Boolean
expression of: A+B = Y. The 2-Inputs OR gate can be built up from the basic NOR
gate with the addition of a NOT gate on the output as shown in Fig 3.4.
Fig 3.4
A simple 2-input logic NOR gate can be constructed using 2 PMOS and 2 NMOS to
connect as shown in the Fig 3.4 with the inputs connected directly to the transistor
bases. The transistor Q1 and Q3 work as a complementary pair, as do transistors Q2
and Q4. Each pair is controlled by a single input signal, where input A will drive the

20
transistor Q1 and Q3, input B will drive the transistor Q2 and Q4. If either input A or
input B are ―high‖ (1), at least one of the NMOS (Q3 or Q4) will be saturated, thus
making the output ―low‖ (0). Only in the event of both inputs being ―low‖ (0) will
both lower transistors be in cut-off mode and both PMOS be saturated, the conditions
necessary for the output to go ―high‖ (1). As mentioned above, when combining the
NOR gate with NOT gate it will become OR gate. The output of NOR gate will
instantaneously become input of NOT gate. The Table 2 shows the truth table for 2-
Inputs OR gate when combining NOR gate with NOT gate.
A B Output for NOR Gate Output for OR Gate
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
Table 2

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3.1.3 Logic AND gate
A Logic AND Gate is a type of digital logic gate that has an output which is normally
at logic level ―0‖ and only goes ―HIGH‖ to a logic level ―1‖ when ALL of its inputs
are at logic level ―1‖. The output state of a ―Logic AND Gate‖ only returns ―LOW‖
again when ANY of its inputs are at a logic level ―0‖. In other words for a logic AND
gate, any LOW input will give a LOW output. The logic or Boolean expression given
for a digital logic AND gate is that for Logical Multiplication which is denoted by a
single dot or full stop symbol, (.) giving us the Boolean expression of: A.B = Y. The
2-Inputs AND gate can be built up from the basic NAND gate with the addition of a
NOT gate on the output as shown in Fig 3.5.
Fig 3.5
Notice how transistors Q1 and Q3 resemble the series-connected complementary pair
from the inverter circuit. Both are controlled by the same input signal (input A), the
upper transistor turning off and the lower transistor turning on when the input is ―high‖
(1), and vice versa. The transistors Q2 and Q4 are similarly controlled by the same
input signal (input B), and how they will also exhibit the same on/off behaviour for
the same input logic levels. The upper transistors of both pairs (Q1 and Q2) have their
source and drain terminals paralleled, while the lower transistors (Q3 and Q4) are

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series-connected. The output will go ―high‖ (1) if either top transistor saturates, and
will go ―low‖ (0) only if both lower transistors saturate. By combining the NAND
gate with NOT gate will become AND gate. The Table 3 shows the truth table for 2-
Inputs AND gate when combining NAND gate with NOT gate.
A B Output for NAND Gate Output for AND Gate
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 3

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3.1.4 3-Inputs OR gate and 3-Inputs AND gate
For the 3-Inputs OR gate and 3-Inputs AND gate, the working theory is the similar as
2-Inputs. The Fig 3.6 and Fig 3.7 are shown the schematic diagram for 3-Inputs OR
gate and 3-Inputs AND gate respectively. The Table 4 and Table 5 show the truth
table for 3-Inputs OR gate and 3-Inputs AND gate respectively.
Fig 3.6
A B C Output for NOR Gate Output for OR Gate
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1
Table 4

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Fig 3.7
A B C Output for NAND Gate Output for AND Gate
0 0 0 1 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
Table 5

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3.1.5 MSBs and LSBs Thermometer Decoder
As 6-bit Current Steering Digital to Analogue Converter (DAC) is implemented in
this project, two set of 3-Bit Binary to Thermometer Decoder are needed to use where
one of them used as 3-Bit MSB and another used as 3-Bit LSB. The schematic is
shown in Fig 3.8. Each of the Thermometer Decoder consists of 7 outputs. DSTM1 is
a digital input which produces a series of binary value into each of the Thermometer
Decoder. It is also used to provide a signal that transition at specific times. As we
need to output the 6 bit which is 26
-1 = 63, therefore STM1 is used as digital input to
generate a total amount of 64 transitions at every 1us. It simply means that the STM1
will increment the value of binary value at every 1us until it finish the loop. The Fig
3.9 shows that the relationship between MSBs and LSBs of Thermometer Decoder.
When the LSB Decoder finished its loop, it will increment the MSB by 1 and the LSB
Decoder will reset from 0 and loop it again.
Fig 3.8: Schematic of MSB and LSB Thermometer Decoder
Fig 3.9
0
VFS
…
Di
Vo
2N
-10
LSB’s
MSB’s

26
Fig 3.10: Schematic of MSB and LSB Thermometer DAC
The DAC has an especially segmented architecture where both the 3 LSBs and the 3
MSBs are converted into thermometer code controlling the current switches. As
shown in the Fig 3.10 above, the outputs of MSB and LSB 3 Bit Thermometer
Decoder will connect with certain input bit of MS DAC and LS DAC. The voltage
and current with name of ―Vbias‖ net alias are maintained in 3.7V and -10uA
respectively. This is because the current source I1 sets the drain current in transistor
M9. This current is then mirrored into the drain of each MSB DAC and LSB DAC.
Besides, cascade current mirror is implemented in order to improve input-output
isolation as there is no direct coupling from the output to input. As we know when
there is an increase of source current it will then increase source-drain voltage as well.
The implementation of this will remove Miller effect and thus provides a higher
bandwidth. A cascade configuration is used to isolate the current source transistor
from the voltage fluctuation at the common node. A small sized cascade transistor is
used to shield the large current source transistor. The current mirror circuit is
connected to the PMOS current cell thereby producing required unit current. With the
help of cascade transistors, the channel length modulation effect which is also known

27
as Miller effect is eliminated in cascade current mirror and output impedance is large
due to cascade transistor present in circuit.
3.2.1 LSB DAC
Fig 3.11: Schematic of LSB Thermometer DAC
As shown in Fig 3.11, a total amount of 28 transistors are used where 14 of them are
PMOS which applied as current source and another 14 are NMOS which implemented
as a control signal. The working principle of the switch is described as,
 If the input is given 0 then NMOS will be in open condition and PMOS will
be in closed condition. Therefore, VDD will then pass through the PMOS and
output is 1.
 If the input is 1 then the PMOS will be in open condition and NMOS will be
in closed condition so the voltage from ground will pass through NMOS and
output is 0.
In this case, PMOS is used as current source that to drive the current from ―Vbias‖ to
be in ready mode. NMOS is used as a control switch and allow the current to flow

28
through it when it is activated. The PMOS will always in saturation mode which is
closed condition so that the drain currents will be in standby mode in each of the
PMOS and ‗wait‘ for activation of NMOS in order to drive the current out to the ―Iout‖.
For example, if SL1, SL2 and SL3 are activated (HIGH), 3 NMOS transistors from
the right will be in closed condition and the drain current of PMOS transistor will be
drive through the NMOS transistor to sum up the total current.
As we can see from the Fig 3.11, an inverter is added to connect with another NMOS
which is connected to the grounded output. This is because switching a current with
only 1 output is more disruptive, and so causes a higher glitch. Therefore, it is
recommend inserting additional grounded output for each inverted input so that the
current switches will be driven simultaneously from parallel latches in order to
minimize the output glitch. This keeps the current source on and properly biased
which, in turn, greatly speeds up the DAC switching and settling.
PMOS switch is used since the VGS value will not be altered due to the output node
voltage changes. The current mirror circuit is connected to the PMOS current cell
thereby producing required unit current. The advantage of PMOS is that the output
sources current and provides a signal which is above ground in a single-supply system.
Why using NMOS as a current switch? This is because for accurate transfer of the
current, source current should equal drain current, and leakage current to control node
should be zero. For NMOS, Vbias should be equal to or greater than Voutput. When
sinking current, VGS will be needed to support Ibias. The formula in below is given to
calculate the total output current for LSB DAC, with given IREF = I1 = 10uA, and N is
resolution of LSB DAC = 3:

29
Since there is only 1 of LSB DAC, the total current output would be 70uA. Taking the
example from above, if the SL1, SL2 and SL3 are activated (HIGH), the total output
current will be equal to 30uA.

30
3.2.2 MSB DAC
Fig 3.12: Schematic of MSB Thermometer DAC
The Fig 3.12 was shown that the internal schematic of MSB DAC. It is completely
difference with LSB DAC as it needed a total amount of 18 transistors for each MSB
DAC where 16 of them are applied as current source and another 2 are implemented
as a control signal. As the same theory in LSB DAC, PMOS is always in saturation
region that prepare the drain current in ready mode. NMOS is used as a control switch
and allow the current to flow through it when it is activated. Note that there are 2
NMOS which one of them which is connected to Iout and the other one is inverted
output which is connected to the ground. As previously discussed, these current
switches must be driven simultaneously from parallel latches in order to reduce the
output glitch. There are total amount of 7 MSB DAC which each of them is connected
by each of the related output of MS_DECODER.

31
The formula in below is given to calculate the total output current for each of MSB
DAC, with given IREF = I1 = 10uA, and N is resolution of LSB DAC = 3:
Since there are total 7 of MSB DAC,
By combining both MSB DAC and LSB DAC together to get the full scale current:
Take a look on Fig 3.10, the calculated Full Scheme Voltage is:

32
IV SIMULATION RESULT
Fig 4.1: Simulation Result of LSB Thermometer Decoder
The Fig 4.1 shows that the transition of 3 bits for LSB Thermometer Decoder from 0s
to 9us with increment of 1us. The binary input value will increment by 1 every 1us.
Consequently, the output which represents by SL1 to SL7 will change its state based
on the binary input value. At initial stage, the binary input value is set as 0. When
binary value change to "001" at 1us, the 1st output SL1 would be triggered up while
the rest still inactivated (1000000); when reached the time 2us where the binary input
is "010", the 2nd output SL2 would be triggered and output SL1 continues activated
(1100000). SL3 will be triggered when it reached 3us and output SL1 and SL2
continues activated (11100000) and so on. Once all the SL is triggered, the binary
value will reset from 0 at 8us and continue to loop it again. This feature has an
advantage in only changing one bit every time to get rid of glitches.

33
Fig 4.2: Simulation Result of MSB Thermometer Decoder
The Fig 4.2 shows that the transition of 3 bits for MSB Thermometer Decoder from 0s
to 63us with increment of 1us. At 8us, all the LSB which are SL1 to SL7 will change
their transition from 1 to 0, and then the 1st bit of MSB which is SM1 will be
activated until the end of the loop. This mean that the related MSB will be activated
every 8us after all the SLs change their state from 1 to 0. The Fig 4.3 was shown the
simulation result of combining both MSB and LSB Thermometer Decoder. In order to
make it clearer, Table 6 and Table 7 are constructed for further understanding.
Fig 4.3: Simulation Result of MSB and LSB Decoder

34
SL7 SL6 SL5 SL4 SL3 SL2 SL1
0us 0 0 0 0 0 0 0
1us 0 0 0 0 0 0 1
2us 0 0 0 0 0 1 1
3us 0 0 0 0 1 1 1
4us 0 0 0 1 1 1 1
5us 0 0 1 1 1 1 1
6us 0 1 1 1 1 1 1
7us 1 1 1 1 1 1 1
Table 6 LSB Thermometer Decoder
SM7 SM6 SM5 SM4 SM3 SM2 SM1
0us 0 0 0 0 0 0 0
8us 0 0 0 0 0 0 1
16us 0 0 0 0 0 1 1
24us 0 0 0 0 1 1 1
32us 0 0 0 1 1 1 1
40us 0 0 1 1 1 1 1
48us 0 1 1 1 1 1 1
56us 1 1 1 1 1 1 1
64us 0 0 0 0 0 0 0
Table 7 MSB Thermometer Decoder

35
Fig 4.4: Simulation Result of MSB and LSB Thermometer DAC
The Fig 4.4 was shown that the outcome of both MSB and LSB Thermometer DAC in
Voltage form. As shown in Fig 4.4, the output is increment like stair look based on
the increases binary input value in every 1us. However, there are still small glitch
existed during all the transition of LSBs from 1 to 0. This is because the current will
immediately drop to 0 when all the transition of all LSBs change from 1 to 0 and then
back to its value again. The IFS and VFS from the Fig 4.4 is exactly the same compare
with theory calculation, which is approximately 630uA and 1.26V respectively.

36
V CONCLUSION
In this thesis, the design, architecture and simulation result of 6 Bit Current Source
Thermometer DAC using Segmented Architecture is presented. To improve the
performance of DAC, a decoder for converting the binary code to the thermometer
code is used. The thermometer code will control the switches of the current source
based to the input code. This architecture utilizes a number of equal-size elements.
Thereby glitches are greatly reduced, hence improving the performance of DAC. The
segmented architecture in this paper is applied by using 2 sets 3 Bit Thermometer
DAC, which 3 Bit for the LSB and another 3 Bit for MSB section in order to achieve
optimum performance with minimum area. This is because the Thermometer-coded
architecture offers the most optimized results in terms of linearity through reducing
the clock feed-through effect especially in switching between multiple transistors.
Differential current steering topology is used in high-speed D/A converters in order to
let all current goes through the output, instead of turning a current off that might cause
the inductive spikes. Besides, cascade current mirror is implemented in this project as
well, in order to reduce the Miller effect that might cause an increase of full scheme
current. The comparison of binary current source DAC and Thermometer coded
current source DAC is explained in this paper. From the analysis, thermometer coded
current source DAC has more advantages than binary DAC. For high resolution,
thermometer DAC is not feasible since the design is complex. Hence for high
resolution DAC, segmented DAC which is the combination of 2 set thermometer
architecture can be used.

37
REFERENCES
1. Aarathi R Krishna, Helna Aboobacker, Remya Jayachandran, ―Design,
Implementation and Comparison of 8 Bit 100 Mhz Current Steering DACs‖
2. Abhijit B. Maidamwar, Vivek P. Landge, ―A Segmented Current Steering DAC
for Wireless Application‖
3. Clayton Hollis Daigle, ―Chapter 3- Current Steering DACs‖
4. James Bryant, Walt Kester, “Chapter 3- Data Converter Architecture”
5. Rahul J. Acharya, ―45-nm CMOS 16-bit Segmented Current-Steering Digital-to-
Analog Converter‖
6. Walt Kester, ―MT014 - Basic DAC Architectures I: String DACs and
Thermometer (Fully Decoded) DACs‖
7. Walt Kester, ―MT016 - Basic DAC Architectures III: Segmented DACs‖
8. Yang Lin, ―Design of a 8-bit CMOS Unit-Element Current-Steering Digital-to-
Analog Converter‖
9. ―CMOS Gate Circuitry‖, Retrieved from
http://www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-circuitry/
10. ―Introduction to Digital Logic Gates‖, Retrieved from http://www.electronics-
tutorials.ws/logic/logic_1.html

38
APPENDICES
Appendix A: Overall Schematic Diagram
Fig 1A: MSB and LSB Current Source Thermometer DAC
Figure 2A: MSB and LSB Thermometer Decoder

39
Appendix B: Internal Schematic Diagram for Decoder and Current Source
DAC
Figure 1B: LSB Thermometer Decoder
Figure 2B: MSB Thermometer Decoder

40
Figure 3B: LSB Current Source Thermometer DAC
Figure 4B: MSB Current Source Thermometer DAC

41
Appendix C: Schematics of Logic Gate in Decoder and Current Source DAC
Figure 1C: NOT Gate
Figure 2C: 2-Inputs OR Gate

42
Figure 3C: 3-Inputs OR Gate
Figure 4C: 2-Inputs AND Gate

43
Figure 5C: 3-Inputs AND Gate

Final Year Report (6bits DACs)

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